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One of the characteristics associated with NAND flash memory is that it only supports a finite number of write cycles. Since the bits in a NAND flash memory block must be erased before new data can be written or programmed to it, the program and erase (P/E) cycles will eventually break down the oxide layer within the floating-gate transistors. Over time, gradual failure of individual flash cells can affect overall performance.

This article discusses those factors associated with SSD flash wear as process geometries get smaller and includes a brief discussion on endurance and reliability tools used to address flash wear, extend drive life and improve data reliability.

HONEY, I SHRUNK THE PROCESS GEOMETRY
As a non-volatile storage technology, NAND flash memory is expensive to produce, requiring ways that will make it more affordable. One way is to shrink the process geometry of the flash itself to obtain more flash dies from a wafer, which in turn, lowers the cost per die. However, the use of smaller process geometries reduces the amount of charge stored per flash cell, as well as cell reliability, making it more difficult to achieve the same working life of the flash in terms of P/E cycles.

Therefore, as process geometries shrink, SSD manufacturers need to address the possible NAND flash wear-out factor through advancements in product architectures, algorithms and controllers. Figure 1 is a quick review of shrinking process geometries since 2009 as it relates to Toshiba NAND flash memory:

A second approach that makes NAND flash memory more affordable is to add an extra bit or two to the original 1-bit NAND flash memory cell (Single Level Cell or SLC) to support 2-bits per cell (Multi-Level Cell or MLC) or 3-bits per cell (Triple Level Cell or TLC). Adding 2 or 3 bits per cell will invariable double or triple flash capacity, however, MLC and TLC will have higher bit error rates than SLC because there are more voltage levels to check and more opportunities to misread a cell's state.

UNDERSTANDING P/E CYCLES
Individual bit cells in NAND flash memory are organised in pages and blocks and as such, are not accessible on a bit per bit basis. Instead, entire blocks or pages are addressed. Today's NAND flash memory is read or programmed on a page basis, typically in sizes of 8KB to 64KB, and erased at a block level, typically in sizes ranging from 1MB to 8MB. To write data to NAND flash memory, an entire block must first be erased before data can be written to it again.

In SSD's, P/E cycles serve as an indicator for quantifying endurance: as each cycle may cause a tiny amount of physical damage to the flash cells, they are capable of a limited number of P/E cycles. This damage may continue and accumulate over time eventually rendering the device unusable. The number of P/E cycles that a given device can sustain before possible problems may ensue varies with the type of NAND flash memory used, as outlined in Fig. 2.

HOW DOES FLASH WEAR?
The strong electrical fields used during P/E cycles are capable of damaging the floating gate and oxide insulator as electrons constantly move into and out of the flash cell substrate. As P/E cycles increase, electrical charges get trapped in the oxide layer distorting the threshold voltage that may eventually cause data errors. Additionally as the P/E count increase, the oxide layer may weaken so that charges on the floating gate may not be retained causing decays and data errors over time.

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